Q.41 Discuss DOS function call and BIOS function call with one example of each. (5)
Ans
DOS function call:
In order to use DOS function calls, always place the function number into register
AH and load all other pertinent information into registers, as described in the entry
data table (Refer Text1-page no 809). Once this is accomplished, follow with an
INT 21H to execute the DOS function.
Example: MOV AH, 6
MOV DL, ‘A’
INT 21H.
Example shows how to display an ASCII A on the CRT screen at the current cursor
position with a DOS function call.
BIO stands for Basic Input Output System. It is aset of programs to provide most
basic low-level services such as services keyboard,disks, serial port, printer, display,
and bootstrap. BIOS programs are stored in a ROM. When power is switched on
ROM-BIOS takes the control of a computer. First of all, ROM-BIOS programs for
power-on-self test are executed. These tests check that whether the computer is in
proper working order after this test, the process of loading the operating system into
main memory is called booting. ROM-BIOS contains a program called bootstrap
loader, this directs CPU to read from the disk a specific program called boot and to
load it into main memory.
BIOS function callsare found stored in the system and video BIOS ROMs. These
BIOS ROM function directly control the I/O devices,with or without DOS loaded
into a system.
INT10H: This is a BIOS interrupt is often called the video services interrupt because
it directly controls the video display in a system. The INT10H instruction uses a
register AH to select video services provided by this interrupt. The video BIOS
ROM is located on the video board and varies from one video card to another.
INT11H: This function used to determine the type of equipment installed in the
system.
INT12H: The memory size is returned by the INT 12H instructions.
INT13H: This call controls the diskettes and alsofixed or hard disk drives attached
to the system.
INT14H: This call controls the serial COM ports attached to the computer.
Q.42 Differentiate between real and protected modes of an Intel microprocessor. Discuss
protected mode memory addressing in brief. (7)
Ans Operation of Real mode interrupt: When the microprocessor completes
executing the current instruction, it determines whether an interrupt is active by
checking (1) instruction execution, (2) single –step, (3) NMI, (4) co-processor
segment overrun, (5) INTR, and (6) INT instruction in the order presented. If one or
more of these interrupt conditions are present, the following sequence of events
occurs:
1. The contents of the flag register are pushed onto the stack
2. Both the interrupt (IF) and trap (TF) flags are cleared. This disables the
INTR pin and the trap or single-step feature.
3. The contents of the code segment register (CS) are pushed onto the
stack.
4. The contents of the instruction pointer (IP) are pushed onto the stack.
5. The interrupt vector contents are fetched, and thenplaced into both IP
and CS so that the next instruction executes at the interrupt service
procedure addressed by the vector.
Protected mode interrupt:
In the protected mode, interrupts have exactly the same assignments as in real
mode, but the interrupt vector table is different. In place of interrupt vectors,
protected mode uses a set of 256 interrupt descriptors that are stored in an
interrupt descriptor table (IDT).
Q.43What do you mean by the term procedure? What is the difference between near
call and far call? (4)
Ans
PROC: The PROC and ENDP directives indicate the start and end of a procedure.
These directives force structure because the procedure is clearly defined. The PROC
directive indicates the start of a procedure, must also be followed with a NEAR or
FAR. A NEAR procedure is one that resides in the same code segment as the
program. A FAR procedure may reside at any locationin the memory system.
Q.44 Design an address decoding logic using a 3:8 decoder (74138) to interface a total of
64k memory locations in the address range from F0000 to FFFFF. Divide 64k
memory locations in eight blocks of 8 k locations each and generate eight chip select
signals. (8)
Ans
Text1-page 350
Q.45 Draw and explain the block diagram of DMA controller. Also explain the various
modes in which DMAC works. (8)
Ans
Direct memory access (DMA) is a process in which an external device takes over
the control of system bus from the CPU.DMA is for high-speed data transfer
from/to mass storage peripherals, e.g. hard disk drive, magnetic tape, CD-ROM, and
sometimes video controllers. For example, a hard disk may boasts a transfer rate of 5
M bytes per second, i.e.1 byte transmission every 200 ns. To make such data transfer
via the CPU is both undesirable and unnecessary.
The basic idea of DMA is to transfer blocks of data directly between memory and
peripherals. The data don’t go through the microprocessor but the data bus is occupied.
“Normal” transfer of one data byte takes up to 29 clock cycles. The DMA transfer
requires only 5 clock cycles.
The modes of operation include demand mode, single mode, block mode, and
cascade mode. Demand mode transfers data until an external EOP is input or until
the DREQ input becomes inactive. Single mode releases the HOLD after each byte
of data transferred. Block mode automatically transfers the number of bytes
indicated by the count register for the channel. Cascade mode is used when more
than one 8237 is present in a system.
Q.46 What is DRAM? What do you understand by DRAM refreshing? With the help of a
block diagram, show how DRAM can be interfaced to amicroprocessor. (6)
Ans Dynamic RAM (DRAM) is essentially the same as SRAM,except that it retains
data for only 2 or 4 ms on an internal capacitor. After 2 or 4 ms, the contents of the
DRAM must be completely rewritten (refreshed) because the capacitors, which store
logic 1 or logic 0, lose their charges. The entire content of the memory is refreshed
with 256 reads in a 2-to-4 ms interval. Refreshing also occurs during a write, a read
or during a special refresh cycle.
Q.47 Discuss mode –2 (bi-directional mode) of 8255 (Programmable Peripheral
Interface). (6)
Q.48 Discuss the following: (ANY THREE) (12)
(i) Some features of Pentium series of microprocessors.
(ii) Virtual memory.
(iii) MMX Technology.
(iv) Graphics adapters.
Ans
(i). Some features of Pentium series of microprocessors:
The Pentium is a 32-bit superscalar, CISC microprocessor. The term superscalar is
used for the processor which contains more than onepipeline to execute more than
one instruction simultaneously in parallel.
The main features of Pentium are, it has two ALU’s,one floating-point unit, two 8
KB cache, pre-fetch buffers, a branch target buffer. Two ALU’s means that there are
two pipelines. Each ALU contains five functional units. The two pipelines are integer
pipelines. They are named U and V pipeline.
When Pentium was introduced, its operating frequency was 60 MHz. gradually; the
operating frequency was raised to 233 MHz. The Pentium uses 0.6 micron Bi-CMOS
process technology. It uses power management feature.
The memory management is improved by adding paging unit and a new system
memory-management mode.
Paging Unit: The paging mechanism functions with 4K– byte memory pages or with
a new extension available to the Pentium with 4M byte-memory pages. In the
Pentium, with the new 4M-byte paging feature memoryfor the page-table reduced to
single page table.
Memory – management mode: The system memory-management mode (SMM) is on
the same level as protected mode, real mode, and virtual mode, but it is provided to
function as a manager. The SMM is not intended to be used as an application or a
system level feature. It is intended for high-level system functions such as power
management.
(ii). Virtual memory:
The term virtual memory refers to something which appears to be present but
actually it is not. The virtual memory technique allows users to use more memory
for a program than the real memory of a computer. A programmer can write a
program which requires more memory space than the capacity of the main
memory. Such a program is executed by virtual memory technique. The program is
stored in the secondary memory. The memory management unit (MMU) transfers
the currently needed part of the program from the secondary memory to the main
memory for execution. This part of the program is executed by the processor. After
execution this part of the program is sent back to the secondary memory together
with the immediate results. Thereafter, the CPU takes another part of the program
for execution. Thus the main memory always keeps only the currently needed part
of the program. This type of ‘to and fro’ movement instructions and data between
the main memory and secondary memory is called swapping. Thus a program
requiring more memory space than the capacity of the main memory can executed
using a swapping technique. This concept is known avirtual memory technique.
(iii). MMX Technology:
MMX (Multimedia extensions) technology adds 57 new instructions to the
instruction set of the Pentium – 4 microprocessors. The MMX technology also
introduces new general purpose instructions. The new MMX instructions are
designed for application such as motion video, combined graphics with video,
image processing, audio synthesis, speech synthesisand compression, telephony,
video conferencing, 2D graphics, and 3D graphics. These new instructions operate
in parallel with other operations as the instruction for the arithmetic coprocessor.
The MMX architecture introduces new packed data types. The data types are eight
packed, consecutive 8-bit bytes; four packed, consecutive 16-bit words; and two
packed, consecutive 32-bit double words.
(iv) Graphics adapters:
Video card converts digital output from the computer into an analog video signal
and sends the signal through a cable to the monitoralso called a graphics card.
• The number of colours a video card displays is determined by its bit depth
• The video card’s bit depth, also called the color depth, is the number of bits it
uses to store information about each pixel
• i.e. 8-bit video card uses 8 bits to store information about each pixel; this video
card can display 256 colors (2x2x2x2x2x2x2x2)
• i.e. 24-bit video card uses 24 bits to store information about each pixel and can
display 16.7 million colors
• The greater the number of bits, the better the resulting image
Video Electronics Standards Association (VESA), which consists of video card
and monitor manufacturers, develops video stands to define the resolution,
number of colors, and other display properties.
a. Monochrome Display Adapter (MDA)
b. Hercules Graphics Card
c. Colour Graphics Adapter (CGA)
d. Enhanced Graphics Adapter (EGA)
e. Video Graphics Adapter (VGA)
f. Super VGA (SVGA) and Other Standards Beyond VGA
Q.49 Write explanatory notes on (ANY FOUR)
(i) Paging
(ii) 8284 Clock generator
(iii) Assembler Directives
(iv) Hard disk drive controller (16)
Ans
(i) Paging:
The memory paging mechanism located within the 80386 and above allows any
physical memory location to be assigned to any linear address. The linear address is
defined as the address generated by a program. Withthe memory paging unit, the
linear address is invisibly translated into any physical address, which allows an
application written to function at a specific address to be located through the paging
mechanism. It also allows memory to be placed into areas where no memory exists.
(ii) 8284 Clock generator:
The 8284 is an ancillary component to the microprocessors. Without clock generator,
many additional circuits are required to generate the clock in an microprocessor
based system. A 8284 provides the following basic functions or signals: Clock
generation, RESET synchronization, READY synchronization, and a TTL-level
peripheral clock signal.
(iii) Assembler Directives:
An assembler directive is a statement to give direction to the assembler to perform
the task of assembly process. The assembler directives control organization of the
program and provide necessary information to the assembler to understand assembly
language programs to generate machine codes. They indicate how an operand or
section of a program is to be processed by the assembler. An assembler supports
directives to define data, to organize segments to control procedures, to define
macros etc.
(iv) Hard disk drive controller: This converts instructions from software running
on the computer to the electrical signals required to operate the hard disk. The
function of a disk controller is disk drive selection, track and sector selection, head
loading, to parallel and parallel to serial conversion of data, error checking etc. The
data recorded on a magnetic disk is the combination of clock and data. Therefore,
data read must be separated from the clock information. The data processed by a CPU
or stored in the main memory is in the byte form. The bytes to be recorded on a
magnetic disk must be converted into serial format.
Q.50 What do you mean by Macro? Discuss merits and dem erits of Macro over
procedures . (6)
Ans MACRO:A sequence of instructions to which a name is assigned is called
macro. Macros and subroutines are similar. Macros are used for short sequence
of instructions whereas subroutines for longer ones. Macros executes faster than
subroutines.
The MACRO directive informs assembler the beginningof a macro This is used
with ENDM directive to enclose a macro. The general format of the MACRO
directive is :
Macro Name MACRO ARG1, ARG2 , …..,ARG N.
The difference is that a procedure is accesses via a CALL instruction, while a
macro and all the instructions defined in the macro, are inserted in the program at
the point of usage. Creating macro is very similar to creating a new op-code that
can be used in the program.
Q.51 Draw and discuss power failure detection circuit interrupt NMI. (6)
Ans
The non-maskable interrupt (NMI) is an edge-triggered input that requests an
interrupt on the positive-edge. After a positive edge, the NMI pin must remain
logic 1 until it is recognized by the microprocessor.
The NMI input is often used for parity errors and other major system faults, such as
power failures. Power failure is easily detected bymonitoring the AC power line
and causing an NMI interrupt whenever AC power drops out. In response to this
type of interrupt, the microprocessor stores all ofthe internal register in a battery
backed-up-memory or an EEPROM. The below fig shows a power failure
detection circuit that provides a logic 1 to the NMI input when ever AC power is
interrupted.
Q.52 Interfaced 2k X 8 (i.e 2716) EPROM using multiple input NAND gate decoder for
memory locations FF800H-FFFFFH. (4)
Ans
Simple NAND gate Decoder: When the 2k x 8 EPROM is used, address
connection A10 – A0 of the 8088 are connected to address inputs A10-A0 of the
EPROM. The remaining nine address pins (A19-A11) are connected to the inputs
of a NAND gate decoder. The decoder selects the EPROM from one of the many
2Kbyte sections of the entire 1Mbyte address range of the 8088 microprocessor.
In this circuit, a single NAND gate decodes the memory address. The output of the
NAND gate is logic 0 whenever the 8088 address pinsattached to its inputs (A19-A11) are all logic 1s. The active low , logic 0 output of the NAND gate decoder is
connected to the CE’ input pin that selects (enables) the EPROM.
Q.53 Explain the functions of the following:
(i) Debugger (ii) Assembler
(iii) Linker (6)
Ans
(i) Debugger: It is a program which allows user to testand debug programs. All
computers including microprocessor kits provide debugging facility. To detect
errors a program can be tested in single steps. Each step of the program is
executed and tested. The debugger allows the user to examine the contents of
registers and memory locations after each step of execution. This also provides
facility to insert breakpoint in the programs.
(ii) Assembler: An assembler or macro-assembler generally forms a part of the
operating system. Which translates a assembly language program into machine
language program.
(iii) Linker: A large program is divided in smaller programs known as modules. A
linker is a program which links smaller programs together to form a large
program. While developing a program subroutines, which are stored in library
file, are frequently used in the program. The linker also links these subroutines
with the main program.
Q.54 Discuss DMA definition and operation in brief (4)
Ans
Direct memory access (DMA) is a process in which an external device takes over
the control of system bus from the CPU.DMA is for high-speed data transfer
from/to mass storage peripherals, e.g. harddisk drive, magnetic tape, CD-ROM,
and sometimes video controllers. For example, a hard disk may boasts a transfer
rate of 5 M bytes per second, i.e.1 byte transmission every 200 ns. To make such
data transfer via the CPU is
both undesirable and unnecessary.
The basic idea of DMA is to transfer blocks of data directly between memory and
peripherals. The data don’t go through the microprocessor but the data bus is
occupied. “Normal” transfer of one data byte takes up to 29 clock cycles. The
DMA transfer requires only 5 clock cycles.
Nowadays, DMA can transfer data as fast as 60 M byte per second. The transfer
rate is limited by the speed of memory and peripheral devices.
Q.55 Write an assembly language program to find average of ‘n’ integers. (6)
Ans
MOV AX, 0000 ; Initial sum 0000
MOV BX, 0000
MOV SI , 0201H
MOV CX, [SI]
BACK: INC SI
INC SI
ADD AX, [SI]
JAE GO
AC23 Microprocessor Based System Design
41
INC BX
GO: LOOP BACK
MOV [0401], AX
MOV [0403], BX
INT 3
Q.56 Explain following instructions in 8086 family with example and their effect on flag.
(i) CWD (ii) IDIV (iii) AAS (iv) SAR
(v) LOOP (vi) SAHF (vii) BOUND (viii) IMUL (12)
Ans
(i) CWD (Convert signed word to signed double word): CWD instruction extends
the sign bit of a word in AX register to all the bits of the DX register. It is used
before a signed word in AX is to be divided by another signed word using
IDIV instruction. No flags are affected.
(ii) IDIV : This instruction is used to divide a 16-bit signed number by an 8-bit
signed number or 32 bit signed number by a 16-bit signed number. The 32 bit
dividend is placed in DX and AX registers. The 16 bit divisor is placed in a
specified 16-bit register or memory locations. No flags are affected.
(iii) AAS: (ASCII adjust after subtraction) It is used toadjust the AX register after a
subtraction operation.
(iv) SAR: (Shift each bit of operand right by specified number of bits), this
instruction shifts each bit of the operand which iscontained in an 8-bit or 16-bit
register or memory locations, right by the specified number of bits. The LSB of
the operand is shifted into carry flag. The MSB which is a sign bit for the sign
operand is retained in MSB position.
Flags affected are: OF, SF, ZF, PF and CF.
(v) LOOP: (Jump to specified label until CX = 0) this isused to repeat a sequence
of instructions for the specified number of times. The number of times the
specified sequence is to be repeated is stored in CX register. No flags are
affected.
(vi) SAHF: (Store AH register into flag register) It is an instruction used to store
the data in the AH register into the lower eight bits of the flag register.
(vii) BOUND: The BOUND instruction, which has two operands, compares a
register with two words of memory data.
(viii) IMUL: This is an instruction for multiplication of two signed numbers. The
result is a signed numbers. The OF (Over flow) andCF (Carry flag) are get
affected.
Q.57 Explain keyboard interfacing to 8088 through 8279. (8)
Ans
The 8279 is a programmable keyboard and display interfacing component that scans
and encodes up to a 64-key keyboard and controls upto a 16-digit numerical display.
The keyboard interface has built in first-in first-out (FIFO) buffer that allows it store
up to eight keystrokes before the microprocessor must retrieve a character. The
display section controls up to 16 numeric displays from an internal 16 X 8 RAM that
stores the coded display information.
The keyboard section consists of eight lines that can be connected to eight columns
of a keyboard, plus two additional lines as well asto shift and CNTL/STB keys. The
key pressed are automatically debounced and the keyboard can operate in two modes
two –key lock out or n-key rollover. If two keys inthe two –key lock out mode are
pressed simultaneously, only first key is recognized. In the N-key roll over mode,
simultaneous key are recognized and their codes arestored in the internal buffer.
Control Word: 000DDMMM - Mode set is command withan op-code of 000 and
two fields programmed to select the mode of operation for the 8279. The DD field
selects the mode of operation for the display and the MMM field selects the mode of
operation for the keyboard.
D7 D6 D5 Function Purpose
0 0 0 Mode Set
Selects the number of display
positions, left or right entry,
and type of keyboard scan.
0 0 1 Clock
Programs the internal clock
and sets the scan and debounce times
0 1 0 Read FIFO
Selects the type of FIFO read
and the address of the read
0 1 1 Read display
Selects the type of display
read and address of the read
1 0 0 Write display
Selects the type of write and
address of the write
1 0 1
Display write
inhibit
Allows half-bytes to be
blanked
1 1 0 Clear Clears the display of FIFO
1 1 1 End interrupt
Clears the IRQ signal to the
microprocessor
The 8279 control word summary
Q.58 Discuss the operation of a real mode interrupt and protected mode interrupt. (6)
Ans Operation of Real mode interrupt: When the microprocessor completes
executing the current instruction, it determines whether an interrupt is active by
checking (1) instruction execution, (2) single –step, (3) NMI, (4) co-processor
segment overrun, (5) INTR, and (6) INT instruction in the order presented. If one or
more of these interrupt conditions are present, the following sequence of events
occurs:
1. The contents of the flag register are pushed onto the stack
2. Both the interrupt (IF) and trap (TF) flags are cleared. This disables the
INTR pin and the trap or single-step feature.
3. The contents of the code segment register (CS) are pushed onto the
stack.
4. The contents of the instruction pointer (IP) are pushed onto the stack.
5. The interrupt vector contents are fetched, and thenplaced into both IP
and CS so that the next instruction executes at the interrupt service
procedure addressed by the vector.
Protected mode interrupt:
In the protected mode, interrupts have exactly the same assignments as in real mode,
but the interrupt vector table is different. In place of interrupt vectors, protected
mode uses a set of 256 interrupt descriptors that are stored in an interrupt descriptor
table (IDT).
Q.59 Write an assembly language program to find one’s complement and two’s
complement of an 8-bit number (4)
Ans
One’s complement of an 8-bit number
LDA 2501H
CMA
STA 2502H
HLT.
Two’s complement of an 8-bit number
LDA 2501H
CMA
INR A
STA 2502H
HLT.
Q.60 Discuss the following terms: (Any six)
(i) Branch prediction logic in Pentium
(ii) Cache structure in Pentium
(iii) Threaded system
(iv) Super scalar architecture
(v) Real time operating system
(vi) D/A conversion (12)
Ans,
(i) Branch prediction logic in Pentium: The Pentium microprocessor uses branch
prediction logic to reduce the time required for a branch caused by internal delays.
These delays are minimized because when a branch instruction is encountered, the
microprocessor begins pre-fetch instruction at the branch address. The instructions are
loaded into the instruction cache, so when the branch occurs, the instructions are
present and allow the branch to execute in one clocking period. If for any reason the
branch prediction logic errors, the branch requires an extra three clocking periods to
execute. In most cases, the branch prediction is correct and no delay ensues.
(ii) Cache structure in Pentium:The cache in the Pentium has been changed from
the one found in the 80486 microprocessor. The Pentium contains two 8K-byte cache
memories instead of one as in the 80486. There is an 8K-byte data cache and an 8Kbyte instruction cache. The instruction cache stores only instructions, while the data
cache stores data used by instructions.
(iii) Threaded system:At times we need to implement an operating system that can
process multiple threads. Multiple threads are handled by the kernel using a real-time
clock interrupt. One method for scheduling processes in a small RTOS is to use a
time slice to switch between various processes. The basic time slice can be any
duration and is some what dependent on the execution speed of the microprocessor.
Each time slice is activated by a timer interrupt. The interrupt service procedure must
look to a queue to see whether a task is available to execute, and if it is, it must start
execution of the new task. If no new task is present, it must continue executing an
old task or enter an idle state and wait for a new task to be queued. The queue is
circular and may contain any number of tasks for the system up to some finite limit.
(iv) Super scalar architecture: The Pentium microprocessor is organized with
three execution units. One executes floating-point instructions, and the other two (Upipe and V-pipe) execute integer instructions. This means that it is possible to
execute three instructions simultaneously.
(v) Real time operating system (RTOS):The RTOS is an operating system used
in embedded applications that performs tasks in a predictable amount of time. RTOS
much like any other operating system in that it contains the same basic sections.
There are three components to all operating systems: (1) initialization, (2) the kernel,
(3) data and procedures. The initialization sectionis used to program all hardware
components in the system, load drivers specific to a system, and program the
contents of the microprocessor’s registers. The kernel performs the basic system
task, provides system calls or functions, and comprises the embedded system. The
data and procedure section holds all procedures and any static data used by the
operating system.
(vi) D/A conversion: Digital-to-analog and analog-to-digital conversions are two
very important aspects of digital data processing. Digital-to-analog involves
conversion of digital data into equivalent analog data. For example, the output of a
digital system might be converted to analog form using a D/A converter for driving a
servomotor, which drives the cursor arm of a plotter or a pen recorder. It clearly
shows in this example DAC emulating decoding deviceaction.
Q.61 Explain explanatory notes on (Any four)
(i) Comparison of RS232C and RS422A standards
(ii) 8259 programmable interrupt controller
(iii) A/D conversion (16)
Ans
(i) Comparison of RS232C and RS422A standards:
RS232C RS422A
1. Standard defined for
asynchronous
communications, where there
is specified timing between
data bits and no fixed timing
between the characters that the
bits form.
2. This standard defined 25
signal lines and 50ft is the
maximum guaranteed distance.
3. This standard defines a serial
system with just a single wire
for each direction.
4. Signal levels are : -25 to -3V
and +3 to +25V.
1. Date Rate : 10 Mbits/s
2. Driving ability upto 4000ft
and 10 receivers
3. It is Differential standard i.e –
Each signal is represented by a
pair of wires and voltage
difference across these wires is
what is sensed at the receiver.
This minimizes the effect of
ground noise or the voltage
drop along the signal leads.
4. Signal levels are : -2 to -6V
and +2 to +6V
(ii) 8259 programmable interrupt controller:
The 8259A adds 8 vectored priority encoded interrupts to the microprocessor. It can
be expanded to 64 interrupt requests by using one master 8259A and 8 slave units.
CS and WR must be decoded. Other connections are direct to microprocessor.
The pins D7 – D0: the bidirectional data connection, IR7 – IR0: Interrupt request,
used to request an interrupt & connect to a slave in a system with multiple 8259A.
WR :-Connects to a write strobe signal (lower or upper in a 16 bit system) , RD :-
Connects to the IORC signal , INT :- Connects to the INTR pin on the
microprocessor from the master and is connected to a IR pin on a slave and INTA
:- Connects to the INTA pin on the microprocessor. In a system only the master
INTA signal is connected
A0 :- Selects different command words with in the 8259A, CS :- Chip select -
enables the 8259A for programming and control, SP/EN :- Slave Program (1 for
master, 0 for slave)/Enable Buffer (controls the data bus transceivers in a large
microprocessor based system when in buffered mode) and CAS2-CAS0 :- Used as
outputs from the master to the slaves in cascaded systems.
Fig : 8259 Block Diagram
(iii) A/D conversion:
Fig : Block Diagram Representation of ADC Operation
The digital inventory are working a revolution in the field of technology,
microcontrollers, microprocessors are used more effectively than those of analog
circuitry. But the output of any sensors, which deals with physical equality like
temperature, humidity, pressure, viscosity, velocity, which are, used most of the data
acquisition flat forms are in the form of analog signals or continuous signals.
Microcontrollers and microprocessors are do nothingwith these signals. Because they
require the signal in the form of binary numbers. So we should convert these analog
signals into digital format. The following popular methods are used for Analog to
Digital conversion.
1. Flash ADC
2. Digital Ramp ADC
AC23 Microprocessor Based System Design
47
3. Successive Approximation ADC
4. Tracking ADC
5. Slope (Integration) ADC.
Q.62 Explain with proper diagram all the six modes of operation of programmable
interval timer 8254. (8)
Ans
Mode 0 - Interrupt on terminal count
Mode 1 - Programmable one-shot
Mode 2 - Rate Generator
Mode 3 - Square wave rate generator
Mode 4 - Software triggered strobe
Mode 5 - Hardware trigger strobe
Mode 0: The output in this mode is initially low, and will remain low for the
duration of the count if GATE = 1.
Width of low pulse = N×T
Where N is the the clock count loaded into counter, and T is the clock period of
the CLK input.
When the terminal count is reached, the output will go high and remain high
until a new control word or new count number is loaded. In this mode, if GATE
input becomes low at the middle of the count, the count will stop and the output
will be low. The count resumes when the gate becomes high again. This in
effect adds to the total time the output is low.
Mode 1: This mode is also called hardware triggerable one-shot.The triggering
must be done through the GATE input by sending a 0-to-1 pulse to it. The
following two steps must be performed:
• Load the count registers.
• A 0-to-1 pulse must be sent to the GATE input to trigger the counter.
Contrast this with mode 0, in which the counter produces the output
immediately after the counter is loaded as long as GATE = 1.In mode 1 after
sending the 0-to-1 pulse to GATE, OUT becomes low and stays low for a
duration of N×T, then becomes high and stays high until the gate is triggered
again.
Mode 2: This mode is also called divide-by-N counter. In this mode, if GATE =
1, OUT will be high for the N×T clock period, goes low for only one clock
pulse, then the count is reloaded automatically, and the process continues
indefinitely.
Mode 3: In this mode if GATE = 1, OUT is a square wave where the high pulse
is equal to the low pulse if N is an even number. In this case the high part and
low part of the pulse have the same duration and are equal to (N/2)×T (50%
duty cycle). If N is an odd number, the high pulse is one clock pulse longer.
This mode is widely used as a frequency divider andaudio-tone generator.
Mode 4: In this mode if GATE = 1, the output will gohigh upon loading the count.
It will stay high for the duration of N×T. After the count reaches zero (terminal
count), it becomes low for one clock pulse, then goes high again and stays high
until a new command word or new count is loaded. Torepeat the strobe, the count
must be reloaded again. Mode 4 is similar to mode 2, except that the counter is not
reloaded automatically. In this mode, the count starts the moment the count is
written into the counter.
Mode 5: This mode is similar to mode 4 except that the trigger must be done with
the GATE input. In this mode after the count is loaded, we must send a low-tohigh pulse to the gate to start the counter.
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