PART V : Microprocessor Questions with Answers
Q.63 What is a macro? Discuss different conditional constructs/statements used while
programming a macro. (4)
Ans MACRO:A sequence of instructions to which a name is assigned is called
macro. Macros and subroutines are similar. Macros are used for short sequence of
instructions whereas subroutines for longer ones. Macros executes faster than
subroutines.
The MACRO directive informs assembler the beginningof a macro This is used
with ENDM directive to enclose a macro. The general format of the MACRO
directive is :
Macro Name MACRO ARG1, ARG2 , …..,ARG N.
Conditional assembly language statements are available for use in the assembly
process and in macro sequences. The conditional statements create instructions that
control the flow of the program and are variations of the IF-THEN, IF-THENELSE, DO-WHILE, and REPEAT-UNTIL constructs used inhigh-level language
programming languages.
; assembled portion with WIDT = TRUE and LENGT=TRUE;
IF WIDT
WIDE DB 72
ELSE
ENDIF
IF LENGT
LONG DB -1
ELSE
ENDIF
Q.64 A 450 ns EPROM won't work directly with a 5MHz 8088.Why? Explain. (2)
AnsWhen the 8088 is operated with a 5 MHz clock, it allows 460 ns for the
memory to access data. Because of the decoder’s added time delay 12ns, it is
impossible for this memory to function within 460 ns.
Q.65 What is an interrupt? Discuss all the five software interrupt instructions. (6)
Ans An interrupt is either a hardware-generated CALL or software-generated
CALL.
The INTEL family microprocessor has software interrupts INT, INT0, INT3
,BOUND and IRET. Out of these five interrupts INT and INT3 are very similar,
BOUND and INT0 are conditional, and IRET is special interrupt return
instruction.
The BOUND instruction, which has two operands, compares a register with two
words of memory data.
INT0 instruction checks the overflow flag (OF). If OF=1, the INT0 instruction
calls the procedure whose address is stored in interrupt vector type number 4. If
OF=0, then the INT0 instruction performs no operation and next sequential
instruction in the program executes.
INT n instruction calls the interrupt service procedure that begins at the address
represented in vector number n. For example, an INT 80H or INT 128 calls the
interrupt service procedure whose address is storedin vector type 80H (000200H –
000203H). To determine the vector address, just multiply the vector number (n) by
4, which gives the beginning address of the 4-byte long interrupt vector. For
example, an INT 5 = 4 x 5 = 20 (14H). The vector for INT5 begins at address
000014H and continues to 000017H. The only exception is the INT3 instruction, a
1-byte instruction.
The IRET instruction is a special return instruction used to return for both software
and hardware interrupts. The IRET instruction is much like a RET, because it
retrieves the return address from the stack.
Q.66 Discuss programmable keyboard and display interface -8279 control word
summary. (8)
Ans,
The 8279 is a programmable keyboard and display interfacing component that
scans up to 64-key keyboard and controls up to a 16-digit numerical display. This
interface has a built-in FIFO (First-In-First-Out) buffer that allows it to store up to
eight keystrokes before the microprocessor must retrieve a character. The display
section controls up to 16 numeric displays from an internal 16 x 8 RAM that stores
the coded display information.
Control Word: 000DDMMM - Mode set is command with an op-code of 000 and
two fields programmed to select the mode of operation for the 8279. The DD field
selects the mode of operation for the display and the MMM field selects the mode
of operation for the keyboard.
D7 D6 D5 Function Purpose
0 0 0 Mode Set
Selects the number of display
positions, left or right entry, and
type of keyboard scan.
0 0 1 Clock
Programs the internal clock and
sets the scan and de-bounce
times
0 1 0 Read FIFO
Selects the type of FIFO read
and the address of the read
0 1 1 Read display
Selects the type of display read
and address of the read
1 0 0 Write display
Selects the type of write and
address of the write
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1 0 1
Display write
inhibit
Allows half-bytes to be blanked
1 1 0 Clear Clears the display of FIFO
1 1 1 End interrupt
Clears the IRQ signal to the
microprocessor
The 8279 control word summary
Q.67 State the importance of PUBLIC, EXTRN directives in modular programming. (4)
Ans The PUBLIC and EXTRN directives are very important to modular
programming. PUBLIC used to declare that labels of code, data, or entire segments
are available to other program modules. EXTRN (external) declares that labels are
external to modules. Without these statements, modules could not be linked together
to create a program by using modular programming techniques. They might link, but
one module would not be able to communicate to another.
The PUBLIC directive is placed in the op-code field of an assembly language
statement to define a label as public, so that the label can be used by other modules.
The EXTRN statement appears in both data and code segments to define labels as
external to the segment. If data are defined as external, their sizes must be defined as
BYTE, WORD or DWORD.
Q.68 What is the main difference between 16 bit and 32 bit versions of C/C++ while using
in line assembler. (4)
Ans The 32-bit applications are written using Microsoft Visual C/C++ for
windows and the 16-bit applications are written using Microsoft C/C++ for DOS. The
main difference is that Visual C/C++ for windows is more common today, but does
not easily call DOS functions such as INT21H.
Q.69 Explain how memory management is improved in Pentium processors? (4)
Ans The memory management is improved by adding paging unit and a new system
memory-management mode.
Paging Unit: The paging mechanism functions with4K – byte memory pages or with a
new extension available to the Pentium with 4M byte-memory pages. In the Pentium,
with the new 4M-byte paging feature memory for the page-table reduced to single
page table.
Memory – management mode: The system memory-management mode (SMM) is on
the same level as protected mode, real mode, and virtual mode, but it is provided to
function as a manager. The SMM is not intended to be used as an application or a
system level feature. It is intended for high-level system functions such as power
management and security, which most Pentiums use during operation.
Q.70 Mention how do the following instructions differ in their functionality- (4)
(i) NEG & NOT (ii) DIV & IDIV
(iii) AND & TEST (iv) CMP & SUB
Ans, NOT: Logical inversion or the one’s complement and NEG: arithmetic
sign inversion or the two’s complement.
DIV: Unsigned numbers division and IDIV: Signed number division.
AND: Performs the AND operation and changes the destination operand. TEST:
Test instruction performs the AND operation and it wont changes destination
operand but it only affects the condition of the flag register.
SUB: Performs the subtraction operation and changes the destination operand.
CMP: Comparison instruction is a subtraction that changes only the flag bits; the
destination operand never changes.
Q.71 Why memory decoding is required? Describe 74LS139 memory decoder (4)
AnsIn order to attach a memory device to the microprocessor, it is necessary to
decode the address sent from the microprocessor. Decoding makes the memory
function at a unique section or partition of the memory map. Without an address
decoder, only one memory device can be connected toa microprocessor, which
would make it virtually useless.
The 74LS139 is a dual 2-to-4 line decoder. It contains two separate 2-to-4 line
decoders – each with its own address, enable, and output connections.
The Pin-out of the 74LS139
Q.72 Explain data addressing modes (with examples) ava ilable in microprocessors.(8)
Ans, Direct Mode:
• Instruction includes memory access.
• CPU accesses that location in memory.
Example:
LDAC 5
Reads the data from memory location 5, and stores the data in the CPU’s
accumulator.
Indirect Mode:
• Address specified in instruction contains address where the operand resides.
Example:
LDAC @5 or LDAC (5)
Retrieves contents of location 5, uses it to accessmemory address.
Register Direct and Register Indirect Modes
• Does not specify a memory address. Instead specifies a register.
Example:
LDAC R
Where R is a register containing the value 5.The instruction copies the value 5 from
register and into the CPU’s accumulator.
Immediate Mode
• The operand specified in this mode is the actual data it self.
Example:
LDAC #5
Moves the value 5 into the accumulator.
Implicit Mode
• Does not exactly specify an operand. Instruction implicitly specifies the
operand because it always applies to a specific register.
Example:
CLAC
Clears the accumulator, and sets value to zero. Nooperands needed.
Relative Mode
• Operand supplied is an offset, not the actual address. Added to the contents
of the CPU’s program counter register to generate the required address.
Example:
LDAC $5 is located at memory location 10, and it takes up two blocks of memory.
Thus the value retrieved for this instruction will be 12 + 5, and will be stored in the
accumulator
Index Mode and Base Address Mode
• Address supplied by the instruction is added to thecontents of an index
register.
• Base address mode is similar except, the index register is replaced by a base
address register.
Example:
LDAC 5(X) where X = 10
Reads data from location (5 + 10) = 15 and stores it in the accumulator.
Q.73 What is the use of these assembler directives-?
(i) .MODEL (ii) PROC (2)
Ans
MACRO:A sequence of instructions to which a name is assigned is called macro.
Macros and subroutines are similar. Macros are used for short sequence of
instructions whereas subroutines for longer ones. Macros executes faster than
subroutines.
The MACRO directive informs assembler the beginningof a macro This is used with
ENDM directive to enclose a macro. The general format of the MACRO directive is:
Macro Name MACRO ARG1, ARG2 , …..,ARG N.
PROC: The PROC and ENDP directives indicate the start and end of a procedure.
These directives force structure because the procedure is clearly defined. The PROC
directive indicates the start of a procedure, must also be followed with a NEAR or
FAR. A NEAR procedure is one that resides in the same code segment as the
program. A FAR procedure may reside at any locationin the memory system.
Q.74 (i) Convert binary number in two's compliment form0100 1000
(ii) Convert hexadecimal BCH to decimal (2)
Ans.
01001000 => 10111000
BCH =>1011 1100 => 188.
Q.75 What is TPA (transient program area)? Draw the memory map of TPA in a personal
computer and explain different areas. (6)
Ans
The memory system is divided into three main parts : TPA, System are and XMS (
extended memory system).
The TPA holds the DOS operating system and other programs that control the
computer system. The TPA also stores any currently active or inactive DOS
application programs. The length of the TPA is 640Kbytes.
9FFFF MSDOS Program
9FFF0
Free TPA
.
.
.
.
.
.
08E30 COMMAND.COM
08490
Device drivers such
as MOUSE.SYS
02530 MSDOS Program
01160 IO.SYS Program
00700
DOS Communication
area
00500
BIOS
Communication area
00400
Interrupt Vectors
00000
The memory map of the TPA in a Personal Computer
Q.76 What is memory paging? Explain how it is used for memory addressing. (6)
Ans
The memory paging mechanism located within the 80386 and above allows any
physical memory location to be assigned to any linear address. The linear address is
defined as the address generated by a program. With the memory paging unit, the
linear address is invisibly translated into any physical address, which allows an
application written to function at a specific address to be located through the paging
mechanism. It also allows memory to be placed into areas where no memory exists.
Q.77 Describe in detail the software interrupts available in INTEL family. How interrupts
are executed in real and protected mode. (8)
Ans
The INTEL family microprocessor has software interrupts INT, INT0, INT3 ,BOUND
and IRET. Out of these five interrupts INT and INT3are very similar, BOUND and
INT0 are conditional, and IRET is special interruptreturn instruction.
The BOUND instruction, which has two operands, compares a register with two words
of memory data.
INT0 instruction checks the overflow flag (OF). If OF=1, the INT0 instruction calls
the procedure whose address is stored in interrupt vector type number 4. If OF=0, then
the INT0 instruction performs no operation and next sequential instruction in the
program executes.
INT n instruction calls the interrupt service procedure that begins at the address
represented in vector number n. For example, an INT 80H or INT 128 calls the
interrupt service procedure whose address is stored in vector type 80H (000200H –
000203H). To determine the vector address, just multiply the vector number (n) by 4,
which gives the beginning address of the 4-byte long interrupt vector. For example, an
INT 5 = 4 x 5 = 20 (14H). The vector for INT5 begins at address 000014H and
continues to 000017H. The only exception is the INT3 instruction, a 1-byte instruction.
The IRET instruction is a special return instruction used to return for both software and
hardware interrupts. The IRET instruction is much like a RET, because it retrieves the
return address from the stack.
Q.78 Explain the necessity of decoding when memory device is attached to a
microprocessor? With neat diagram indicate how a simple NAND gate decoder is used
to select a 2716 EPROM memory component for memory locations FF800H-FFFFFH.
(5)
Ans
In order to attach a memory device to the microprocessor, it is necessary to decode the
address sent from the microprocessor. Decoding makes the memory function at a
unique section or partition of the memory map. Without an address decoder, only one
memory device can be connected to a microprocessor,which would make it virtually
useless.
Simple NAND gate Decoder: When the 2k x 8 EPROM is used, address connection
A10 – A0 of the 8088 are connected to address inputs A10-A0 of the EPROM. The
remaining nine address pins (A19-A11) are connectedto the inputs of a NAND gate
decoder. The decoder selects the EPROM from one of the many 2Kbyte sections of the
entire 1Mbyte address range of the 8088 microprocessor.
In this circuit, a single NAND gate decodes the memory address. The output of the
NAND gate is logic 0 whenever the 8088 address pinsattached to its inputs (A19-A11)
are all logic 1s. The active low , logic 0 output of the NAND gate decoder is connected
to the CE’ input pin that selects (enables) the EPROM.
Q.79 Write a Program in assembly language to find the largest of n numbers stored in the
memory. (8)
Ans
MOV AX, 0000
MOV SI, 0200
MOV CX, [SI]
BACK : INC SI
INC SI
CMP AX, [SI]
JAE GO
MOV AX, [SI]
GO: LOOP BACK
MOV [0251], AX
INT 3.
Q.80 Define the following (3)
(i) Isolated I/O (ii) memory mapped I/O
(iii) Hand shaking
Ans
There are two schemes for the allocation of addresses to memories and input /
output devices.
(i). Memory Mapped I/O Scheme: In this scheme there is only one address
space. Address space is defined as all possible addresses that microprocessor can
generate. Some addresses are assigned to memories and some addresses to I/O
devices. An I/O device is also treated as a memory location and one address is
assigned to it. In this scheme all the data transfer instructions of the
microprocessor can be used for both memory as well as I/O device. This scheme
is suitable for a small system.
(ii). In I/O mapped I/O scheme the addresses assigned to memory locations can
also be assigned to I/O devices. Since the same address may be assigned to a
memory location or an I/O device, the microprocessor must issue a signal to
distinguish whether the address on the address bus is for a memory location or an
I/O device.
(iii). Hand shaking: In an ASYNCHRONOUS data transfer is not based on
predetermined timing pattern. This technique of data transfer is used when the
speed of an I/O device does not match the speed of the microprocessor, and the
timing characteristic of I/O device is not predictable. In this technique the status
of the I/O device i.e. whether the device is ready or not, is checked by the
microprocessor before the data are transferred. The microprocessor initiates the
I/O device to get ready and then continuously checks the status of the I/O device
till the I/O device becomes ready to transfer data. When I/O device becomes
ready, the microprocessor sends instructions to transfer data. This mode of data
transfer is also called handshaking mode of data transfer. The microprocessor
issues an initiating signal to the I/O device to get ready. When I/O device
becomes ready it sends signals to the processor to indicate that it is ready. Such
signals are calledhandshake signals.
Q.82 What is the function of 8254 Programmable IntervalTimer? Discuss any one of its
applications in detail. (8)
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Ans
• 8253/54 Timer Description and Initialization
• PTI (programmable Interval Timer/Counter)
• 8253 and 8254 have exactly the same pin-out.
• 8254 is a superset of the 8253.
• It Generates accurate time delays
• It can be used for applications such as a real-time clock, an event
counter, a digital one shot, a square wave generator and a complex
waveform generator
8254 Functional Description:
8254 Programming:
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8254 Mode1 Operation:
Q.83 Discuss the control words (ICWS) of IC8259. (5)
Ans
The Programmable interrupt controller is used when several I/O devices transfer data
using interrupt and they are connected to the same interrupt line of the
microprocessor.
The Intel 8259 is a single chip programmable interrupt controller. It is compatible
with 8086, 8088 and 8085 microprocessor. It is a 28–pin DIP I.C package and uses
N-MOS technology.
8259 Control Word Initialization
Q.84 Write short note on “ANY FOUR” of the following (16)
(i) ISA BUS
(ii). Graphic Adapter and MONITOR
(iii). DMA controller
(iv). Protected mode addressing
Ans
(i) The ISA or Industry Standard Architecture, bus has been around since the
very start of the IBM-compatible personal computer system. In fact, any card
from the very first personal computer will plug into and function in any of the
modern Pentium 4-based computers. This is all made possible by the ISA bus
interface found in all these machines, which is still compatible with the early
personal computers.
ISA bus has evolved from its original 8-bit standard to the 16-bit standard found
in most systems today. The ISA bus connector contains the entire demultiplexed address bus (A19-A0) for the 1M byte 8088 system, the 8-bit data
bus (D7-D0), and the four control signals MEMR’, MEMW’, IOR’ and IOW’
for controlling I/O and any memory that might be placed on the printed circuit
card. ISA Card only operates at 8 MHz rate.
(ii) Video card converts digital output from the computer into an analog video
signal and sends the signal through a cable to the monitor also called a graphics
card.
• The number of colors a video card displays is determined by its bit depth
• The video card’s bit depth, also called the color depth, is the number of bits
it uses to store information about each pixel
• i.e. 8-bit video card uses 8 bits to store information about each pixel; this
video card can display 256 colors (2x2x2x2x2x2x2x2)
• i.e. 24-bit video card uses 24 bits to store information about each pixel and
can display 16.7 million colors
• The greater the number of bits, the better the resulting image
Video Electronics Standards Association (VESA), which consists of video card
and monitor manufacturers, develops video stands to define the resolution,
number of colors, and other display properties.
g. Monochrome Display Adapter (MDA)
h. Hercules Graphics Card
i. Color Graphics Adapter (CGA)
j. Enhanced Graphics Adapter (EGA)
k. Video Graphics Adapter (VGA)
l. Super VGA (SVGA) and Other Standards Beyond VGA
(iii) A DMA controller interfaces with several peripherals that may request
DMA. The controller decides the priority of simultaneous DMA requests
communicates with the peripheral and the CPU, and provides memory addresses
for data transfer. DMA controller commonly used with 8088 is the 8237
programmable device.
The 8237 is in fact a special-purpose microprocessor. Normally it appears as
part of the system controller chip-sets. The 8237 is a 4-channel device. Each
channel is dedicated to a specific peripheral device and capable of addressing 64
K bytes section of memory.
(iv). This addressing allows access to data and programs located above the first
1M byte of memory, as well as within the first 1M byte of memory. Addressing
this extended section of the memory system requires a change to the segment
plus an offset addressing scheme used with real mode memory addressing. When
data and programs are addressed in extended memory,the offset address is still
used to access information located within the memory segment.
The segment register contains a selector that selects a descriptor from a
descriptor table. The descriptor describes the memory segment’s location,
length, and access rights.
Q.85 Compare RS232C and RS422A standards.
Ans
RS232C RS422A
1. Standard defined for
asynchronous communications,
where there is specified timing
between data bits and no fixed
timing between the characters
that the bits form.
2. This standard defined 25
signal lines and 50ft is the
maximum guaranteed distance.
3. This standard defines a serial
system with just a single wire for
each direction.
4. Signal levels are : -25 to -3V
and +3 to +25V.
1. Date Rate : 10 Mbits/s
2. Driving ability upto 4000ft
and 10 receivers
3. It is Differential standard
i.e – Each signal is represented by
a pair of wires and voltage
difference across these wires is
what is sensed at the receiver.
This minimizes the effect of
ground noise or the voltage drop
along the signal leads.
4. Signal levels are : -2 to -6V and +2 to +6V
Q.86 Discuss the feature of Pentium in brief.
HRQ
HLDA
DRQ
DACK
PI/E
Controler DMA Dispozitiv Periferic
Memoria
principala
HOLD
U C P
MA
MD
MC
HOLDA
Magistrala de adrese
Magistrala de date
Magistrala de comenzi
Ans
The Pentium is a 32-bit superscalar, CISC microprocessor. The term superscalar is
used for the processor which contains more than onepipeline to execute more than
one instruction simultaneously in parallel.
The main features of Pentium are, it has two ALU’s,one floating-point unit, two 8
KB cache, pre-fetch buffers, a branch target buffer. Two ALU’s means that there
are two pipelines. Each ALU contains five functional units. The two pipelines are
integer pipelines. They are named U and V pipeline.
When Pentium was introduced, its operating frequency was 60 MHz. gradually; the
operating frequency was raised to 233 MHz. The Pentium uses 0.6 micron BiCMOS process technology. It uses power management feature.
Q.87 Discuss the following assembler directives with example
i. DWORD
ii. OFFSET
iii. SEGMENT
iv. MACRO
v. ASSUME
vi. ENDP
Ans
(i). DWORD:It defines word type variable. The defined variable may have one or
more initial values in the directive statement. If there is one value, two bytes of
memory space are reserved. The general format is
Name of variable DW Initial value or values.
(ii). OFFSET: It is an operator to determine the offset (displacement) of a variable
or procedure with respect to the base of the segment which contains the named
variable or procedure. The operator can be used to load a register with the offset
of a variable.
The operator can be used as follows :
MOV SI, OFFSET ARRAY
(iii). SEGMENT : This directive defines to the assembler the start of a
segment with name segment-name. The segment name should be unique and
follows the rules of the assembler
The Syntax is as follows:
Segment Name SEGMENT {Operand (Optional)} ; Comment
.
.
.
Segment Name ENDS.
(iv). MACRO: A sequence of instructions to which a name is assigned is
called macro. Macros and subroutines are similar. Macros are used for short
sequence of instructions whereas subroutines for longer ones. Macros executes
faster than subroutines.
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The MACRO directive informs assembler the beginning of a macro This is used
with ENDM directive to enclose a macro. The general format of the MACRO
directive is :
Macro Name MACRO ARG1, ARG2 , …..,ARG N.
(v). ASSUME: This directive will be used to map the segment register names with
memory addresses.
The Syntax is as follows:
ASSUME SS: Stackseg, DS : Dataseg, CS:Codeseg
The ASSUME will tell the assembler to use the SS register with the address of the
stack segment whose name is stackseg.
(vi). ENDP: (End Procedure) It informs assembler the end of a procedure. In
assembly language programming, subroutines are called procedures. A procedure
may be an independent program module to give certain result or the required value
to the calling program. This directive is used together with PROC directive to
enclose procedure. The general format of ENDP directive is:
Procedure Name ENDP
Q.88 Discuss Stepper motor interfaced to the 82C55.
Ans
A stepper motor rotates in steps in response to digital pulse input. The shaft of the
motor rotates in equal increments when a train of input pulses is applied. To control
direction, numbers of steps to appropriate pulses are applied to the stator windings
of the motor.
12 V supply is used to energize the poles. Pulses sent by the microprocessor switch
on rated voltage to the windings of the desired poles. A delay subroutine is
incorporated in the program. After energizing one set of pole windings some delay
is provided, then the power supply is switched ontothe other set of pole windings.
This delay governs the speed of motor.
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Q.89 Discuss the EISA bus and need of PCI bus.
Ans
The Extended Industry Standard Architecture (EISA) is a 32 bit modification to the
ISA bus. As computers became larger and had wider data buses, a new bus was
needed that would transfer 32-bit data. The clocking speed limited up to 8MHz.
The most common application for the EISA bus is a disk controller or as a video
graphics adapter. These applications benefit from the wider data bus width because
the data transfer rate for these devices are high.
Peripheral Component Interconnect (PCI): This bus was developed by Intel and
introduced in 1993. It is geared specifically to fifth- and sixth-generation systems,
although the latest generation 486 motherboards usePCI as well.
PCI bus has plug – and – play characteristics and the ability to function with a 64-bit data bus. A PCI interface contains series of registers, located in a small memory
device on the PCI interface, that contains information about the board.
Q.90 Explain cascading of multiple PIC 8259.
Ans
The 8259A adds 8 vectored priority encoded interrupts to the microprocessor. It can
be expanded to 64 interrupt requests by using one master 8259A and 8 slave units.
CS and WR must be decoded. Other connections are direct to microprocessor.
The pins D7 – D0: the bidirectional data connection, IR7 – IR0: Interrupt request,
used to request an interrupt & connect to a slave in a system with multiple 8259A.
WR :-Connects to a write strobe signal (lower or upper in a 16 bit system) , RD :-
Connects to the IORC signal , INT :- Connects to the INTR pin on the
microprocessor from the master and is connected to a IR pin on a slave and INTA
:- Connects to the INTA pin on the microprocessor. In a system only the master
INTA signal is connected
Fig: 8259 Pin Diagram
A0:- Selects different command words with in the 8259A, CS :- Chip select -
enables the 8259A for programming and control, SP/EN :- Slave Program (1 for
master, 0 for slave)/Enable Buffer (controls the data bus transceivers in a large
microprocessor based system when in buffered mode) and CAS2-CAS0 :- Used as
outputs from the master to the slaves in cascaded systems.
Fig: cascading multiple 8259
Q.91 Discuss need of Pipelining and Caches.
Ans
The simplest technique for improving performance through hardware parallelism is
pipelining. Pipelining consists of breaking up the operations to be performed into
simpler independent operations, sort of like the breaking up the operations of
assembling a car in an assembly line. A typical processor pipeline consists of 4
pipeline stages (1) Instruction fetch, (2) Instruction decode (3) Instruction execute
and (4) Register file write-back/memory access. In practice however, real
architectures have many more physical pipeline stages, with multiple physical
stages corresponding to one of the above stages. For example the execute stage
might occupy 4 physical pipeline stages
The primary advantages of pipelining are
- Parallelism
- Smaller cycles time
Caches are the other big thing done in the last 2 decades to improve performance.
Keep things locally if they are going to be used soon. From a physics point of view,
an access to memory which is almost exclusively offchip will mean signals have to
travel that much further in one cycle. In practice,since we do not want to make the
system as slow as its slowest component (memory), and the cycle time is not
determined by the memory access time, and rather memory takes several cycles to
complete.
Q.92 Explain in brief steps to develop a Microprocessor based computer system
Ans
The design of a microcomputer system must begin with the CPU module. This
module establishes the basic system timing, providean orderly means of starting up
the processor, and provide access to the system buses.
The second step is adding Memory, it is essential to the stored program computer.
From this unit that the CPU fetches instructions directing it in some task. But within
a particular computer system there may be several types of memories each with its
own hierarchy.
The third step is adding input / output: This is also known has user interface.
There are basically two hardware techniques for getting data into and out of a
computer. The first is the parallel interface and is the most natural for
microprocessor. The second technique is the serial interface
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