Q.12 What is the difference between XT and AT computer system? (2)
Ans
XT ->extended and AT->Advanced Technology
Some differences between the PC and XT include the type of power supply
originally included--63 vs 135 watts; the number and spacing of expansion
slots--5 vs 8; the PC has a cassette tape interfaceconnector on the back.
Q.13 What are program-invisible registers? (2)
Ansthe global and local descriptor tables are found in the memory system. In
order to access and specify the address of these tables, the program invisible
registers used. The program invisible registers are not directly addressed by
software so they are given name.
The GDTR (global descriptor table register) and IDTR (interrupt descriptor
table register) contain the base addresses of the descriptor table and its limit.
The limit of each descriptor table is 16 bits because the maximum table length is
64 Kbytes. When the protected mode operation is desired, the address of the
global descriptor table and its limit are loaded into the GDTR.
Q.14 The interrupt vector table is always created in thefirst 1K area of the memory.
Justify the statement. (2)
AnsWhen the CPU receives an interrupt type number from the PIC, it uses this
number to look up the corresponding interrupt vector in memory. There are 256
interrupt types. Each interrupt vector occupies 4 bytes. Therefore, a total of 4 x
256 = 1K bytes of memory is reserved at the beginning of the processor memory
address space for storing interrupt vectors.
Q.15 What is the purpose of carry (c) flag and zero (z) flag? (2)
AnsCarry flag holds the carry after addition or the borrow after subtraction. The
carry flag also indicates error conditions, as dictated by some programs and
procedures.
The Zero flag shows that the result of an arithmetic or logical operation is zero.
If Z=1, the result is zero; if Z=0, the result is notzero.
Q.16 What is 16-bit ISA? Compare it with 8-bit ISA bus. (6)
AnsThe only difference between the 8 and 16-bit ISA bus is that an additional
connector is attached behind the 8-bit connector. 16-bit ISA card contains two
edge connectors. One plugs into the original 8-bit connector and other plugs into
the 16-bit connector. The added features that are most often used are the
additional interrupt request inputs and DMA request signals. Interfaces found
for the ISA bus are modems and sound cards.
Q.17 Compare memory mapped I/O with I/O mapped I/O. (4)
Ans Memory Mapped I/O Scheme: In this scheme there is only one address
space. Address space is defined as all possible addresses that microprocessor
can generate. Some addresses are assigned to memories and some addresses to
I/O devices. An I/O device is also treated as a memory location and one address
is assigned to it. In this scheme all the data transfer instructions of the
microprocessor can be used for both memory as well as I/O device. This scheme
is suitable for a small system.
In I/O mapped I/O scheme the addresses assigned to memory locations can also
be assigned to I/O devices. Since the same address may be assigned to a
memory location or an I/O device, the microprocessor must issue a signal to
distinguish whether the address on the address bus is for a memory location or
an I/O device.
Q.18 Explain in brief the functions of the clock gener ator chip, 8284. (4)
Ans, 8284 Clock generator:
The 8284 is an ancillary component to the microprocessors. Without clock
generator, many additional circuits are required to generate the clock in an
microprocessor based system. A 8284 provides the following basic functions or
signals: Clock generation, RESET synchronization, READY synchronization,
and a TTL-level peripheral clock signal.
Q.19 Write a brief note on MMX technology. (4)
Ans, MMX (Multimedia extensions) technology adds 57 new instructions to the
instruction set of the Pentium – 4 microprocessors.The MMX technology also
introduces new general purpose instructions. The new MMX instructions are
designed for application such as motion video, combined graphics with video,
image processing, audio synthesis, speech synthesis and compression,
telephony, video conferencing, 2D graphics, and 3D graphics. These new
instructions operate in parallel with other operations as the instruction for the
arithmetic coprocessor.
The MMX architecture introduces new packed data types. The data types are
eight packed, consecutive 8-bit bytes; four packed, consecutive 16-bit words;
and two packed, consecutive 32-bit double words.
Q.20 What are the different modes in which 8255 Programmable Peripheral Interface
(PPI) can operate? Write the 8086 initialisation routine required to program
8255 for mode 1 with Port A and Port B as output Ports and Port C as an input
port. Indicate all the relevant signals. (6)
Ans
• 24 I/O lines in 3 8-bit port groups – A, B, C
• A, B can be 8-bit input or output ports
• C can serve as 2 4-bit input or output ports
• 3 modes of operation:
– Mode 0:A, B, C simple input or output level sensitive ports
– Mode 1:A, B input or output ports with strobe control in C
– Mode 2:A is bidirectional with control/handshake inB and C
• A, B can only change 1 byte at a time
• C has individual bit set/reset capability
• Advantage is non-dedicated circuit can change port configuration with
software and no “glue logic”
• Ports A, B, and C are used for I/O data.
• The control register is programmed to select the operation mode of the three
ports A, B, and C.
• Mode 0 : simple I/O mode
• Any of the ports A, B, CL and CU can be programmed as input or output.
• No control of individual bits (all bits are out or all bits are in)
Mode0:
Mode1:
Mode2:
Q.21 Explain the operation of IRET instruction. What memory locations contain the
vector for an INT 34 instruction? (4)
Ans
The Interrupt return (IRET) instruction is used only with software or hardware
interrupt service procedures. Whenever an IRET instruction executes, it stores
the contents of I and T from the stack. This is important because it preserves the
state of the flag bits. If interrupts were enabled before an interrupt service
procedure, they automatically re-enabled by the IRET instruction because it
restores the flag register.
Interrupt Number 20-FF are stored at an address 80 – 3FFH.
Q.22 Explain the following terms:
i. Branch prediction logic.
ii. Paging.
iii. Assembler.
iv. Microprocessor development system. (8)
Ans
(i) Branch prediction logic in Pentium: The Pentium microprocessor uses
branch prediction logic to reduce the time required for a branch caused by
internal delays. These delays are minimized becausewhen a branch instruction is
encountered, the microprocessor begins pre-fetch instruction at the branch
address. The instructions are loaded into the instruction cache, so when the
branch occurs, the instructions are present and allow the branch to execute in one
clocking period. If for any reason the branch prediction logic errors, the branch
requires an extra three clocking periods to execute. In most cases, the branch
prediction is correct and no delay ensues.
(ii) Paging Unit: The paging mechanism functions with 4K – byte memory
pages or with a new extension available to the Pentium with 4M byte-memory
pages. In the Pentium, with the new 4M-byte paging feature memory for the
page-table reduced to single page table.
(iii) Assembler:An assembler or macro-assembler generally forms a part of the
operating system. Which translates a assembly language program into machine
language program.
(iv) Microprocessor development system:Computer systems have undergone
many changes recently. Machines that once filled large areas have been reduced
to small desktop computer systems because of the microprocessor. Although
these desktop computers are compact, they possess computing power that was
only dreamed of a few years ago.
The blocks of the microprocessor based system are
1. The Memory and I/O System
2. The DOS Operating System
3. The Microprocessor
Q.23 Explain the following instructions:
(i) TEST (ii) NEG (iii) CMP (iv) DAA. (8)
Ans
(i) TEST: The TEST instruction performs the AND operation. The difference is
that the AND instruction changes the destination operand, while the TEST
instruction does not. A TEST only affects the condition of the flag register,
which indicates the result of the test.
(ii) NEG: Arithmetic sign inversion or two’s complement (NEG). The NEG
instruction two’s complements a number, which meansthat the arithmetic sign of
a signed number changes from positive to negative or from negative to positive.
(iii)CMP: The comparison instruction (CMP) is a subtraction that changes only
the flag bits; the destination operand never changes. A comparison is useful for
checking the entire contents of a register or a memory location against another
value. A CMP is normally followed by a conditional jump instruction, which
tests the condition of the flag bits
(iv) DAA: The DAA instruction follows the ADD or ADC instruction to adjust
the result into a BCD result. The DAA instruction functions only with the AL
register, this addition must occur eight bits at a time.
Q.24 With respect to serial communication define the following:
(i) baud rate. (ii) asynchronous communication.
(iii) parity. (iv) half duplex. (4)
Ans
Half Duplex Transmission: A half duplex channel can send and receive, but not
at the same time. It’s like a one-lane bridge where two-way traffic must give
way in order to cross. Only one end transmits at a time, the other end receives.
Asynchronous means "no synchronization", and thus does not require sending
and receiving idle characters. However, the beginning and end of each byte of
data must be identified by start and stop bits. Thestart bit indicates when the
data byte is about to begin and the stop bit signals when it ends. The
requirement to send these additional two bits causes asynchronous
communication to be slightly slower than synchronous however it has the
advantage that the processor does not have to deal with the additional idle
characters.
The rate of data transfer in serial data communication is denoted in bps. Bits per
second (bps) is the rate of transfer of informationbits. Baud is the number of
signal level changes per second in a line, regardless of the information content
of those signals. The baud and bps rates are not necessarily equal. The ratio of
BPS to baud depends on the information-coding scheme that you are using. For
example, each character in asynchronous RS-232 coding includes a start and
stop bit that are not counted as information bits, so the BPS rate is actually less
than the baud rate.
Besides the synchronization provided by the use of start and stop bits, an
additional bit called a parity bit may optionally be transmitted along with the
data. Figure shows the inclusion of an additional parity bit for error control
purposes. A parity bit affords a small amount of error checking, to help detect
data corruption that might occur during transmission. You can choose even
parity, odd parity, mark parity, space parity or none at all. When even or odd
parity is being used, the numbers of marks (logical1 bit) in each data byte are
counted, and a single bit is transmitted following the data bits to indicate
whether the number of 1 bit just sent is even or odd.
Fig. Framed data including a parity bit
For example, when even parity is chosen, the parity bit is transmitted with a
value of 0 if the number of preceding marks is an even number. For the binary
value of 0110 0011 the parity bit would be 0. If even parity were in effect and
the binary number 1101 0110 were sent, then the parity bit would be 1.
Q.25 What is the importance of RS232-C in serial communication? Name some
application where you see its use. (4)
'B'
D7 D6 D5 D4 D3 D2 D1 D0
'C' 'A'
Stop
bit
Start
bit
Character frame,11 bits in total
Parity
bit
P
Ans RS-232 stands for Recommend Standard number 232 and C is the latest
revision of the standard. The serial ports on most computers use a subset of the
RS-232C standard. The full RS-232C standard specifies a 25-pin "D" connector
of which 22 pins are used. Most of these pins are not needed for normal PC
communications, and indeed, most new PCs are equipped with male D type
connectors having only 9 pins. In the world of serial communications, there are
two different kinds of equipment:
• DTE - Data Terminal Equipment
• DCE - Data Communications Equipment
Q.26 Write short notes on (Any FOUR):-
(i) 8259.
(ii) Real time clock.
(iii) Real and protected mode.
(iv) Super scalar architecture.
(v) Comparison between Motorola processors and INTEL processors.
(4 x 4 = 16)
Ans
(i) 8259:
The 8259A adds 8 vectored priority encoded interrupts to the microprocessor. It can
be expanded to 64 interrupt requests by using one master 8259A and 8 slave units.
CS and WR must be decoded. Other connections are direct to microprocessor.
The pins D7 – D0: the bidirectional data connection, IR7 – IR0: Interrupt request,
used to request an interrupt & connect to a slave in a system with multiple 8259A.
WR :-Connects to a write strobe signal (lower or upper in a 16 bit system) , RD :-
Connects to the IORC signal , INT :- Connects to the INTR pin on the
microprocessor from the master and is connected to a IR pin on a slave and INTA
:- Connects to the INTA pin on the microprocessor. In a system only the master
INTA signal is connected
A0 :- Selects different command words with in the 8259A, CS :- Chip select -
enables the 8259A for programming and control, SP/EN :- Slave Program (1 for
master, 0 for slave)/Enable Buffer (controls the data bus transceivers in a large
microprocessor based system when in buffered mode) and CAS2-CAS0 :- Used as
outputs from the master to the slaves in cascaded systems.
Fig : 8259 Block Diagram
(ii) Real time clock:
A real-time clock keeps the time in real time – that is, in hours and minutes. The
software for the real-time clock contains an interrupt service procedure that is
called 60 times per second and a procedure that updates the count located in four
memory locations.
Assembler directives:
An assembler directive is a statement to give direction to the assembler to
perform the task of assembly process. The assembler directives control
organization of the program and provide necessary information to the assembler
to understand assembly language programs to generate machine codes. They
indicate how an operand or section of a program is to be processed by the
assembler. An assembler supports directives to define data, to organize
segments to control procedures, to define macros etc.
(iii) Real and protected mode:
Operation of Real mode interrupt: When the microprocessor completes
executing the current instruction, it determines whether an interrupt is active by
checking (1) instruction execution, (2) single –step, (3) NMI, (4) co-processor
segment overrun, (5) INTR, and (6) INT instruction in the order presented. If
one or more of these interrupt conditions are present, the following sequence of
events occurs:
1. The contents of the flag register are pushed onto the stack
2. Both the interrupt (IF) and trap (TF) flags are cleared. This disables the
INTR pin and the trap or single-step feature.
3. The contents of the code segment register (CS) are pushed onto the
stack.
4. The contents of the instruction pointer (IP) are pushed onto the stack.
5. The interrupt vector contents are fetched, and thenplaced into both IP
and CS so that the next instruction executes at the interrupt service
procedure addressed by the vector.
Protected mode interrupt:
In the protected mode, interrupts have exactly the same assignments as in real
mode, but the interrupt vector table is different. In place of interrupt vectors,
protected mode uses a set of 256 interrupt descriptors that are stored in an
interrupt descriptor table (IDT).
(iv). Super scalar architecture:
The Pentium microprocessor is organized with three execution units. One
executes floating-point instructions, and the other two (U-pipe and V-pipe)
execute integer instructions. This means that it is possible to execute three
instructions simultaneously.
(v). Comparison between Motorola processors and INTEL processors:
AMD/Intel processors are really about the same thing. They run the same
software and operate in a very similar manner. AMD is often less expensive
than Intel, and depending on what you use a computer for one may be somewhat
faster than the other.
Motorola has been largely relegated to the "also-ran" category of
microprocessor manufactures since Apple computer stopped using them in favor
of the IBM Power PC processor (Apple has since switched to Intel).
Motorola had an excellent 32 bit processor design years before Intel.
Furthermore, the design of the Motorola 68000 processor line (from a
programmer's perspective) was immensely better. The two major features of the
68000 line that made this true were
1) Orthogonality of register access and
2) Number of registers available.
These features made writing code for Motorola CPUs much simpler.
Q.27 What is (i) USB (ii) AGP (iii) XMS (iv) EMS (v) TSR (vi) EDO RAM (6)
Ans
(i). USB:The USB (UNIVERSAL SERIAL BUS) is intended to connect
peripheral devices such as keyboards, a mouse, modems, and sound cards to
the microprocessor through a serial data path and atwisted pair of wires. The
main idea is to reduce system cost by reducing the number of wires. Another
advantage is that the sound system can have a separate power supply from the
PC, which means less noise. The data transfer rates through the USB are 12
Mbps at present.
(ii). AGP:The latest addition to many computer systems is the inclusion
of the accelerated graphics port(AGP). The AGP operates at the bus clock
frequency of the microprocessor. It is designed so that a transfer between the
video card and the system memory can progress at a maximum speed. The
AGP can transfer data at a maximum rate of 528M bytes per second. This port
probably will never be used for any devices other than the video card.
(iii). XMS:The memory system is divided into three main parts. TPA
(transient program area), system area, and XMS (extended memory
system). The type of microprocessor in your computer determines whether an
extended memory system exists.
(iv). EMS:The area at location C8000H-DFFFFFH is often open or free.
This area is used for the expanded memory systemin a PC or XT system, or
for the upper memory system in an AT system. The EMS allows a 64K-byte
page frame of memory to be used by application programs.
(v). TSR:The TPA also holds TSR (terminate and stay resident) programs
that remain in memory in an active state until activated by a hot-key sequence
or another event such as an interrupt.
(vi). EDO RAM:A slight modification to the structure of the DRAM
changes the device into an EDO (extended data output) DRAM device. In the
EDO memory, any memory access, including a refresh, stores the 256 bits
selected by RAS’ into latches. These latches hold the next 256 bits of
information, so in most programs, which are sequentially executed, that data
are available without any wait states.
Q.28 What are program invisible registers? Explain the purpose of the GDTR. If the
microprocessor sends linear address 00200000H to the paging mechanism,
which paging directory entry and which page table entry is accessed? (3)
Ans, the global and local descriptor tables are found in the memory system. In
order to access and specify the address of these tables, the program invisible
registers used. The program invisible registers are not directly addressed by
software so they are given name.
The GDTR (global descriptor table register) and IDTR (interrupt descriptor
table register) contain the base addresses of the descriptor table and its limit.
The limit of each descriptor table is 16 bits because the maximum table length is
64 Kbytes. When the protected mode operation is desired, the address of the
global descriptor table and its limit are loaded into the GDTR.
For linear address 00000000H – 003FFFFFH, the first entry of the page
directory is accessed. Each page directory entry represents or repages a 4-Mbyte
section of the memory system. The contents of the page directory select a page
table that is indexed by the next 10 bits of the linear address. This means that
address 00000000H – 00000FFFH selects page directory entry 0 and page table
entry 0.
Q.29 Discuss the salient features of a parallel programmable interface, 8255. (4)
Ans
• 24 I/O lines in 3 8-bit port groups – A, B, C
• A, B can be 8-bit input or output ports
• C can serve as 2 4-bit input or output ports
• 3 modes of operation:
– Mode 0:A, B, C simple input or output level sensitive ports
– Mode 1:A, B input or output ports with strobe control in C
– Mode 2:A is bidirectional with control/handshake inB and C
• A, B can only change 1 byte at a time
• C has individual bit set/reset capability
• Advantage is non-dedicated circuit can change port configuration with
software and no “glue logic”
• Ports A, B, and C are used for I/O data.
• The control register is programmed to select the operation mode of the three
ports A, B, and C.
• Mode 0 : simple I/O mode
• Any of the ports A, B, CL and CU can be programmed as input or output.
• No control of individual bits (all bits are out or all bits are in)
• Mode 1: Ports A and B can be used as input or output ports with
handshaking.
• Mode 2 : Port A can be used as bidirectional I/O port with handshaking
Q.30 What do you understand by assembler directives? What do the following
assembler directives do?
(i) ASSUME
(ii) SEGMENT
(iii) DB
(iv) PUBLIC (8)
Ans
(i) ASSUME: This directive will be used to map the segment register names
with memory addresses.
The Syntax is as follows:
ASSUME SS: Stackseg, DS : Dataseg, CS:Codeseg
The ASSUME will tell the assembler to use the SS register with the address of the stack
segment whose name is stackseg.
(ii) SEGMENT: This directive defines to the assembler the start of a segment with
name segment-name. The segment name should be unique and follows the rules of the
assembler
The Syntax is as follows:
Segment Name SEGMENT {Operand (Optional)} ; Comment
.
.
.
Segment Name ENDS.
(iii) DB (Define Byte): The DB directive defines a byte-type variable (i.e. a
variable which occupies one byte of memory space). In a given directive statement,
there may be single initial value or multiple values of the defined variable. If there is
one initial value, one byte of memory space is reserved. If there are multiple values,
one byte of memory space is reserved for each value. The general format is:
Name of Variable DB Initial value or values.
(iv) The PUBLIC and EXTRN directives are very important to modular
programming. PUBLIC used to declare that labels of code, data, or entire segments
are available to other program modules. EXTRN (external) declares that labels are
external to modules. Without these statements, modules could not be linked together
to create a program by using modular programming techniques. They might link, but
one module would not be able to communicate to another.
The PUBLIC directive is placed in the opcode field of an assembly language
statement to define a label as public, so that the label can be used by other modules.
Q.31 Discuss the role of a bus arbiter in a multiprocessor configuration. (4)
Ans, Bus arbiter: Which functions to resolve priority between bus masters and
allows only one device at a time to access the shared bus. The 8289 bus arbiter
controls the interface of a bus master to a shared bus. This is designed to function
with the 8086/8088 microprocessors. Each bus masteror microprocessor requires an
arbiter for the interface to the shared bus, which Intel calls the MULTIBUS and IBM
calls the MICRO CHANNEL.
The shared bus used only to pass information from one microprocessor to another;
otherwise, the bus master function in their own local bus modes by using their own
local programs, memory, and I/O space. Microprocessors connected in this kind of
system are often called parallel or distributed processors because they can execute
software and perform tasks in parallel.
Q.32 Show how a typical DMA controller can be interfac ed to an 8086/8085 based
maximum mode system. (8)
Ans, For 8088 in maximum mode:
The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receive
acknowledge signals. Sequence of events of a typical DMA process
1) Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has
higher priority)
2) 8088 completes its current bus cycle and enters into a HOLD state
3) 8088 grants the right of bus control by asserting a grant signal via the same pin as
the request signal.
4) DMA operation starts
5) Upon completion of the DMA operation, the peripheral asserts the request/grant
pin again to relinquish bus control.
Q.33 What is a co-processor? What is its use in a typical microprocessor based
system. (8)
Ans8087 NDP (numerical data processor) is also known as math co-processor
which is used in parallel with the main processor for number crunching
applications, which would otherwise require complex programming. It is also
faster than 8086/8088 processor in performing mathematical computation. It has
its own specialized instruction sets to handle mathematical programs.
It is a processor which works in parallel with the main processor. It has its own
set of specialized instructions. The number crunching part of the program is
executed by 8087. Instruction for 8087 are written in the main program
interspersed with the 8086 instructions. All the 8087 instruction codes have
11011 as the most significant bits of their first code byte.
Q.34 What is segmentation? What are its advantages? How is segmentation
implemented in typical microprocessors? (8)
Ans
Segment memory addressing divides the memory into many segments. Each of these
segments can be considered as a linear memory space. Each of these segment is
addressed by a segment register.
However since the segment register is 16 bit wide and the memory needs 20 bits for
an address the 8086 appends four bits segment register to obtain the segment
address. Therefore, to address the segment 10000H by , say the SS register, the SS
must contain 1000H.
The first advantage that memory segmentation has isthat only 16 bit registers are
required both to store segment base address as wellas offset address. This makes the
internal circuitry easier to built as it removes the requirement for 20 bits register in
case the linear addressing method is used. The second advantage is relocatability.
Q.35 What is a PCI bus? Discuss its features and usage. (6)
Ans
Peripheral Component Interconnect (PCI): This bus was developed by Intel and
introduced in 1993. It is geared specifically to fifth- and sixth-generation systems,
although the latest generation 486 motherboards usePCI as well.
PCI bus has plug – and – play characteristics and the ability to function with a 64-bit
data bus. A PCI interface contains series of registers, located in a small memory device
on the PCI interface that contains information about the board.
Q.36 How is EISA bus different from ISA bus? (4)
Ans
The Extended Industry Standard Architecture (EISA) is a 32 bit modification to the ISA
bus. As computers became larger and had wider data buses, a new bus was needed that
would transfer 32-bit data. The clocking speed limited up to 8MHz. The most common
application for the EISA bus is a disk controller or as a video graphics adapter. These
applications benefit from the wider data bus width because the data transfer rate for
these devices are high.
Q.37 Differentiate between synchronous and asynchronoustypes of serial communication.
(6)
Ans Serial data communication uses two basic types, synchronous and
asynchronous. With synchronous communications, the two devices initially
synchronize themselves to each other, and then continually send characters to stay in
sync. Even when data is not really being sent, a constant flow of bits allows each
device to know where the other is at any given time. That is, each character that is
sent is either actual data or an idle character.
Asynchronous means "no synchronization", and thus does not require sending and
receiving idle characters. However, the beginning and end of each byte of data must be
identified by start and stop bits. The start bit indicates when the data byte is about to
begin and the stop bit signals when it ends. The requirement to send these additional
two bits causes asynchronous communication to be slightly slower than synchronous
however it has the advantage that the processor does not have to deal with the
additional idle characters.
Q.38 Draw and explain the block diagram of programmable interrupt controller 8259.
(8)
Ans The 8259A adds 8 vectored priority encoded interrupts to the
microprocessor. It can be expanded to 64 interrupt requests by using one master
8259A and 8 slave units. CS and WR must be decoded.Other connections are
direct to microprocessor.
The pins D7 – D0: the bidirectional data connection, IR7 – IR0: Interrupt request,
used to request an interrupt & connect to a slave in a system with multiple 8259A.
WR :-Connects to a write strobe signal (lower or upper in a 16 bit system) , RD :-
Connects to the IORC signal , INT :- Connects to the INTR pin on the
microprocessor from the master and is connected to a IR pin on a slave and INTA
:- Connects to the INTA pin on the microprocessor. In a system only the master
INTA signal is connected
A0 :- Selects different command words with in the 8259A, CS :- Chip select -
enables the 8259A for programming and control, SP/EN :- Slave Program (1 for
master, 0 for slave)/Enable Buffer (controls the data bus transceivers in a large
microprocessor based system when in buffered mode) and CAS2-CAS0 :- Used as
outputs from the master to the slaves in cascaded systems.
Fig : 8259 Block Diagram
Q.39 Discuss the various types of memory devices that you are familiar with. (8)
Ans
All of the memory used as main store in a modern computer is implemented as
semiconductors fabricated on wafers of silicon. Semiconductor memory is fast and
easy to use. To fulfil the needs of modern computer systems it is becoming
increasingly dense (more bits per chip) and cheap.
A semiconductor memory chip consists of a large number of cells organized into
an array, and the logic necessary to access any array in the cell easily. Semiconductor memory may be classed according to the mechanism used by each cell
to store data. The simplest type of memory is called static memory. In static
memory each cell uses a flip-flop made from four orsix transistors. The data in
each cell is remembered until the power is switchedoff. Static memory is easy to
use and reliable, but is relatively bulky, slow and expensive. Most computer
systems therefore use dynamic memory as their main store.
Dynamic memory uses
just a single transistor per cell, and is therefore denser, faster and cheaper.
Unfortunately each cell gradually forgets the data stored in it, and so extra circuitry
must be used to continually refresh the cells.
Memory, with regard to computers, most commonly refers to semiconductor
devices whose contents can be accessed (i.e., read and written to) at extremely high
speeds. The main characteristics of semiconductor memory are based on capacity,
organization and access time. In microprocessor-based systems semiconductor
memories are used as primary storage for code and data.
In contrasts with storage, which (1) retains programs and data regardless of
whether they are currently in use or not, (2) retains programs and data after the
power supply has been disconnected, (3) has much slower access speeds and (4)
has a much larger capacity (and a much lower cost).Examples of storage devices
are hard disk drives (HDD), floppy disks, optical disks (e.g., CDROMS and
DVDs) and magnetic tape.
The term memory as used in a computer context originally referred to the magnetic
core memory devices that were used beginning in the1950s. It was subsequently
applied to the semiconductor memory devices that replaced core memories in the
1970s.
Computer memory today consists mainly of dynamic random access memory
(DRAM) chips that have been built into multi-chip modules that are, in turn,
plugged into slots on the motherboard (the main circuit board on personal
computers and workstations). This DRAM is commonly referred to as RAM
(random access memory), and it constitutes the mainmemory of a computer.
The random in random access memory refers to the fact that any location in such
memory can be addressed directly at any time. This contrasts with sequential
access media, such as magnetic tape, which must be read partially in sequence
regardless of the desired content.
There are three basic kinds of memory used in microprocessor systems -
commonly called ROM, RAM, and hybrid. ROM and RAM are - "Read Only
Memory" and "Random Access Memory". The program maybe stored in ROM or
RAM - the program does not normally change while it executes - while data is
stored in the registers and RAM. Of course, if you turn off the chip and turn it on
again, you have lost all the contents of the registers, and RAM.
In a typical computer, as much as possible is in RAM, to give the maximum
possible flexibility; you have basic programmes allowing you to interact with
discs, keyboards and the display in ROM, and load in as much of the software as
possible when you run the programs.
Q.40 Write explanatory notes on Microprocessor development system. (16)
Ans,
Microprocessor development system:
Computer systems have undergone many changes recently. Machines that once
filled large areas have been reduced to small desktop computer systems because of
the microprocessor. Although these desktop computers are compact, they possess
computing power that was only dreamed of a few years ago.
The blocks of the microprocessor based system are
1. The Memory and I/O System
2. The DOS Operating System
3. The Microprocessor
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